Home
Clock
Registers
Arithmetic logic unit
Random Access Memory
Program Counter
Output register
Control logic
Full CPU
How does the output module work?
Output with display
−
100%
+
Fit
Reset
CLK
0
'CLR
0
OI
0
SIGNED
0
◆ BUS0
Z
◆ BUS1
Z
◆ BUS2
Z
◆ BUS3
Z
◆ BUS4
Z
◆ BUS5
Z
◆ BUS6
Z
◆ BUS7
Z
⏸
timer
1.5 ms