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Clock
Registers
Arithmetic logic unit
Random Access Memory
Program Counter
Output register
Control logic
Full CPU
How do the registers work?
Register A & B
Instruction Register
Register A & B
Register with Transceiver
−
100%
+
Fit
Reset
Clock
0
Clear
0
Load (AI_n)
0
Output Enable (AO_n)
0
◆ BUS0
Z
◆ BUS1
Z
◆ BUS2
Z
◆ BUS3
Z
◆ BUS4
Z
◆ BUS5
Z
◆ BUS6
Z
◆ BUS7
Z
Instruction Register
Instruction Register with Transceiver
−
100%
+
Fit
Reset
Clock
0
Clear
0
'II
0
'IO
0
◆ BUS0
Z
◆ BUS1
Z
◆ BUS2
Z
◆ BUS3
Z
◆ BUS4
Z
◆ BUS5
Z
◆ BUS6
Z
◆ BUS7
Z